Analog to digital converters, and particularly that class of converters known as the successive approximation type, are typically comprised of a preamplifier stage, often termed the instrumentation amplifier, a sample and hold circuit, and an encoder.
The instrumentation amplifier functions to condition the analog input signal to be compatible with the encoder wherein it is converted to digital form. In most data acquisition systems in common use today, the system multiplexer produces a double ended or differential output voltage. The encoder responds to a signal ended signal and thus signal conversion is necessary. The instrumentation amplifier operates to provide differential to signal ended signal conversion, as well as common mode signal rejection with whatever voltage gain is needed to provide a single ended output voltage range that is compatible with the sample and hold and encoder circuitry which follow in that order.
Typically, an instrumentation amplifier consists of an input transconductance amplifier and an output transimpedance amplifier. The transconductance amplifier converts a difference in voltage at its two inputs into a current at its output. Voltages common to both inputs do not produce an output current. Thus, the transconductance amplifier rejects voltages common to both its input terminals. Its output current is then fed into the transimpedance amplifier, which is referenced to the data acquisition system ground, to convert it back into an output voltage. Since this output voltage is referenced to the data acquisition system ground, it is called single-ended. The voltage gain of the instrumentation amplifier is set by the product of the input stage transconductance and the output stage transimpedance. The gain may be altered by changing the transconductance, the transimpedance, or both.
The voltage out of the instrumentation amplifier is sampled at a defined time by the sample and hold circuit and held as a fixed DC voltage at its output while the encoder converts it into a digital signal. A typical sample and hold circuit consists of an input buffer amplifier, an electronic switch, a holding capacitor and an output buffer amplifier. The input buffer amplifier may be omitted if the transimpedance stage of the instrumentation amplifier can withstand the transient produced by the electronic switch and hold capacitor combination.
The output voltage from the sample and hold circuit is applied to the encoder input. A typical encoder of the successive approximation type consists of an input stage, a decoder, a comparator, a latch, sequential logic, and a voltage reference. The input stage may be a precision resistor or may be a buffer amplifier driving a precision resistor. The decoder is a digital to analog converter. The latch operates to store the binary output state of the comparator while the sequential logic operates to generate digital input to the decoder. The voltage reference functions to set the digital to analog conversion range of the decoder. The operation of the encoder generally follows the following sequence. The input stage converts the sample and hold output voltage into a current which is compared against a current generated by the decoder. The currents are compared at a node called the summing node or summing bus. The comparator output is a digital signal which is queried and stored in the latch, after allowing time for the comparator to settle. The output from the latch is fed to the sequential logic and tells it whether the decoder output current is larger than the signal current. If it is, the last digit to be entered into the decoder, is switched back to a zero and the next smaller digit is entered. If it is not, the last digit to be entered is kept, and the next smaller digit is entered. After allowing it time to settle again, the comparator is queried, and its decision stored in the latch, and so on, repetitively, until the least significant digit has been compared to end the decoding process.
It is known that analog to digital converters experience offset and gain errors. Offset error is defined as a translation error. This means that it is a constant error regardless of signal magnitude. Gain error is defined as a slope error. This means that it is a linear function of signal magnitude. In that offset error and gain error are two separate and distinct entities, they must be individually correct.
In conventional analog to digital converters using a separate instrumentation amplifier and a separate sample and hold circuit distinct from the encoder circuit, offset error is generally corrected only at the instrumentation amplifier. This is accomplished during an offset correction period of an encoding cycle by tying the differential voltage signal inputs of the instrumentation amplifier together, and/or ground, and driving the output to zero by means of a separate offset correction sample and hold amplifier whose inputs tie to system ground and the instrumentation amplifier output, and whose output is a bias current change in the front end of the transconductance stage of the instrumentation stage of the amplifier. During the zeroing operation, the sample switch of the correction sample and hold circuit is closed. When it is opened, the offset correction is held while the inputs to the instrumentation amplifier are tied to the signal source through the multiplexer of the data acquisition system. This scheme leaves the output of the instrumentation amplifier offset by an amount equal to the offset of the correction sample and hold circuit.
The technique just described is but one of the known techniques which make use of the instrumentation amplifier for offset correction. It is also known to provide offset correction with respect to the encoder alone or the encoder and sample and hold circuit together. Such known offset correction schemes employ a correction loop around the encoder or around the encoder and sample and hold circuits together. Such correction loops may employ correction circuits such as the one discussed with respect to the instrumentation amplifier offset correction circuit or they may employ digital correction and storage in the encoder itself.
Gain correction is not often done in the analog portion of the data acquisition system. The more common practice is to apply a standard signal to one multiplexer channel, encode it, take the digital difference between what is encoded and what would have been, and in the digital processor part of the system, calculate a multiplication factor from this difference. This multiplication factor is then used to multiply the succeeding channel codes.
For a more complete understanding of the state of the prior art, reference is made to FIGS. 1 and 2. FIG. 1 illustrates a conventional analog to digital converter forming a part of a data acquisition system. FIG. 2 illustrates specific circuitry which might be used to implement the functional blocks of FIG. 1. The instrumentation amplifier, sample and hold circuit, and encoder of FIG. 1 are constructed as distinct circuits and are produced as separate modules, printed circuit boards or integrated circuits.
The input switches 10 include input signal switches S.sub.V and S'.sub.V as well as system ground switches S.sub.G and S'.sub.G. Thus, the differential input signal from the multiplexer portion of the data acquisition system is applied to the input of the transconductance amplifier 12 through the signal switches S.sub.V and S'.sub.V. At certain times during the conversion sequence, such as during offset correction, it is necessary for the inputs to the transconductance amplifier to be tied to the data acquisition system ground. Switches S.sub.G and S'.sub.G provide this ability.
The transconductance amplifier 12 as illustrated in FIG. 2 is but one of several such amplifiers which may be used with the analog to digital converter. The illustrated transconductance amplifier includes differential amplifiers 46, 48 which receive the differential input signal from the system multiplexer. The transconductance amplifier further includes current sources 40 and 42, current mirror 44, and current mirrors 50 and 52. The transconductance amplifier gain is given by the reciprocal of the value of the resistance R.sub.G1. The value of the resistance R.sub.G1 can be switched to change the voltage range at the input.
The purpose of the current mirrors 44, 50 and 52 in the transconductance amplifier is to permit the differential input to single ended output conversion with common mode signal voltage rejection. The output from the transconductance amplifier is taken at a node 56. Thus, the amplifier 12 operates as a voltage to current converter to thereby supply a single ended current signal proportional to the differential input voltage at the node 56. This current is supplied to the transimpedance amplifier 14.
The transimpedance amplifier may comprise a differential amplifier A1 with feedback resistance R.sub.2. The value of the resistance R.sub.2 determines the gain of the transimpedance amplifier 14. The transimpedance amplifier operates as a current to voltage converter to produce the required voltage signal to the input of the signal sample and hold circuit 18.
The signal sample and hold circuit stores the voltage at the output of the transimpedance amplifier 14 on its holding capacitor C.sub.1 when the sample switch S.sub.S closes and holds this voltage after the switch opens. This voltage is transferred through a unity gain buffer amplifier A.sub.2 to the transconductance stage 24 of the encoder. The transconductance stage illustrated in FIG. 2, is simply a resistor R.sub.G2 whose output end ties to the summing node 25 of the encoder. The summing node is maintained at virtual ground and is held at ground potential by negative feedback through the nonlinear network 58 comprised of two anode to cathode parallel connected diodes. The output of the transconductance stage is thus the current equal to the signal sample and hold voltage times the reciprocal of the value of the resistance R.sub.G2.
In normal operation, the current flowing into the summing node 25 is successively compared against current generated by the decoder 26 which flows out of the summing node during the encoding process.
Mention has not yet been made of offset correction as implemented in the prior art circuits of FIGS. 1 and 2. In the conventional analog to digital converter system of the type being discussed, offset correction is oftentimes provided for in the instrumentation amplifier alone. It is accomplished by means of a sample and hold circuit 16 which feeds back around the transimpedance amplifier. During the correction portion of the encoding cycle, the input switches tie both inputs to the transconductance amplifier to system ground. That is, during the offset correction sequence of the operating cycle, switches S.sub.V and S'.sub.V are open while switches S.sub.G and S'.sub.G are closed. This sequencing of the switches is illustrated in the switch timing diagram of FIG. 5. As a result, any offsets in the transconductance amplifier 12 produce an output current at the inverting input to the transimpedance amplifier 14. The product of this current and the resistance R.sub.2 produces a voltage at the output of the transimpedance amplifier. During the offset correction sequence, the switch S2 of the amplifier A3 is open while switches 21 and S3 are closed to close the correction loop. The offset correctional operational amplifier A3 then drives the holding capacitor C2 through the switch S3 to a voltage that will permit the MOSFET buffer stage 54 to sink offset current, thereby forcing the output of the transimpedance amplifier 14 to zero. Switches S1 and S3 are then opened, leaving the correction signal stored as a voltage across the capacitor C2. The switch S2 is closed to keep the amplifier A3 from running into stops and saturating some bipolar device which would cause an unnecessarily long recovery time. The switching sequence for switches S1, S2, and S3 are illustrated in the switch timing diagram of FIG. 5.
In operation of the analog to digital converter system of FIGS. 1 and 2, signal sample and hold occurs after offset correction during an operating cycle. Following the sampling and holding on capacitor C1 of the voltage proportional to the differential input voltage, the encoding sequence begins. The encoding sequence is conventional and well known to those skilled in the art.
It should now become apparent from the preceding discussion that the input signal to be converted to digital form has twice been converted from a voltage to a current, once in the instrumentation amplifier, and once in the encoder. It would indeed be advantageous if this duplication could be eliminated while substantially simplifying the circuitry of the analog to digital converter.